Discussion:
aarch64: Don't .set a symbol named st2
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Martin Storsjö
2017-12-25 19:40:03 UTC
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x264 | branch: master | Martin Storsjö <***@martin.st> | Mon Oct 16 22:50:25 2017 +0300| [12ca9a69e855c4d4b9000894f478bce665e4e02c] | committer: Anton Mitrofanov

aarch64: Don't .set a symbol named st2

This confuses gas-preprocessor, which tries to replace actual
st2 instructions by the integer 1 or 2.
http://git.videolan.org/gitweb.cgi/x264.git/?a=commit;h=12ca9a69e855c4d4b9000894f478bce665e4e02c
---

common/aarch64/mc-a.S | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)

diff --git a/common/aarch64/mc-a.S b/common/aarch64/mc-a.S
index 179215fb..e2f2c492 100644
--- a/common/aarch64/mc-a.S
+++ b/common/aarch64/mc-a.S
@@ -718,9 +718,9 @@ endfunc
function mc_chroma_w\width\()_neon
// since the element size varies, there's a different index for the 2nd store
.if \width == 4
- .set st2, 1
+ .set idx2, 1
.else
- .set st2, 2
+ .set idx2, 2
.endif
CHROMA_MC_START
b.eq 2f
@@ -785,10 +785,10 @@ function mc_chroma_w\width\()_neon
//pld [x3]
//pld [x3, x4]

- st1 {v16.\vsize}[0], [x0], x2
- st1 {v16.\vsize}[st2], [x1], x2
- st1 {v17.\vsize}[0], [x0], x2
- st1 {v17.\vsize}[st2], [x1], x2
+ st1 {v16.\vsize}[0], [x0], x2
+ st1 {v16.\vsize}[idx2], [x1], x2
+ st1 {v17.\vsize}[0], [x0], x2
+ st1 {v17.\vsize}[idx2], [x1], x2
b.gt 1b

ret
@@ -820,10 +820,10 @@ function mc_chroma_w\width\()_neon
//pld [x3]
//pld [x3, x4]

- st1 {v16.\vsize}[0], [x0], x2
- st1 {v16.\vsize}[st2], [x0], x2
- st1 {v17.\vsize}[0], [x1], x2
- st1 {v17.\vsize}[st2], [x1], x2
+ st1 {v16.\vsize}[0], [x0], x2
+ st1 {v16.\vsize}[idx2], [x0], x2
+ st1 {v17.\vsize}[0], [x1], x2
+ st1 {v17.\vsize}[idx2], [x1], x2
b.gt 3b

ret
@@ -853,10 +853,10 @@ function mc_chroma_w\width\()_neon
//pld [x3]
//pld [x3, x4]

- st1 {v16.\vsize}[0], [x0], x2
- st1 {v16.\vsize}[st2], [x0], x2
- st1 {v17.\vsize}[0], [x1], x2
- st1 {v17.\vsize}[st2], [x1], x2
+ st1 {v16.\vsize}[0], [x0], x2
+ st1 {v16.\vsize}[idx2], [x0], x2
+ st1 {v17.\vsize}[0], [x1], x2
+ st1 {v17.\vsize}[idx2], [x1], x2
b.gt 5b

ret

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